Operation of logic circuits for computer and peripheral devices often requires the use of two or more clocks. Often a single logic circuit is interfaced to two or more other circuits or devices operating at different clock frequencies. Synchronous operation of the logic circuit with the interfaced circuits is often required. Therefore, clocking for the logic circuit must be switched to the clock frequency of the interfaced circuit requiring synchronous operation.
The switching between clocks of varying frequency or phase often results in transients in clocking of the logic circuit. These transients may be induced by mixing of two or more clock signals or by a simultaneous enablement or disablement of the various clocks. Due to the presence of delay and settling time in the elements of the logic circuit itself, such transients may induce errors or indeterminant states in the logic circuit. Recent prior art circuits for clock switching have provided synchronization for enablement and disablement of the various clocks. Such a prior art circuit is shown in FIG. 1.
In the prior art shown a selection signal for the clock was synchronized through strings of two or more serially connected D-type flip-flops. Each string is clocked by one clock. The output from these flip-flops is connected to an AND gate with the selected clock to provide an enabled clock output. Disabling of the clock not selected is accomplished by extracting the intermediate output of the serial flip-flops and tying that signal into the AND gate with the clock. Enablement of the clock is thereby synchronized to the second clock pulse after selection while disablement of the clock is synchronized to the first clock pulse after selection. Outputs of the AND gates for enabled or disabled clocks are connected through an OR gate to provide the selected clock to the logic circuit.
While the example prior art device does provide synchronization of the enable and disable signals with each individual clock, it is possible for a clock of lower frequency to remain enabled while a higher frequency clock also becomes enabled, thus causing a transient pulse on the output. Providing additional serial flip-flops in the synchronizer for the higher frequency clock may eliminate this transient behavior. However, clock switching times are then limited to the worst case timing imposed by the pulse duration of the low frequency clock. In the prior art example shown, clock 1 is the higher frequency clock and therefore requires a three flip-flop synchronizer. Clock 2, the lower frequency clock, requires two serial flip-flops for synchronization.
A disparity in clock frequency of a factor of 5 or greater is not uncommon in current computer and peripheral design. This disparity would result in strings of 5 or 6 serial flip-flops for enabling the foster clock in the prior art example.
Additionally, in many applications the absence of one of the clock signals may be likely. The sensing of the presence of the enabled clock is necessary for automatic or program controlled response to the lack of a selected clock. The example prior art circuit does not provide this capability.